Electrical systems in motor vehicles are subject to a variety of fault conditions that produce a wide spectrum of potentials at the output of electrical devices such as integrated circuits ("ICs"). For example, in large measure due to the different ground potentials occurring throughout the vehicle chassis, a short to ground fault may result in a potential in the range of zero to -1 or -2 Volts relative to the ground of an IC exposed to the fault. Likewise, because motor vehicle electrical systems may operate from either unswitched battery or switched battery, the output of an IC may be shorted to the battery supply even when no supply voltage is electrically connected to the IC. Of course, the output device in electrical devices such as ICs must be protected against damage by such faults.
A common IC output device employed in motor vehicle electrical systems is the vertical pnp transistor. The damage such devices may incur as a result of the various possible faults will depend upon the device's external electrical connection, internal geometry and biasing. Typically a vertical pnp transistor used as an output transistor will be externally electrically connected in a common emitter configuration with its emitter electrically connected to the supply and its collector electrically connected to the output. Moreover, in junction isolation devices the p-substrate is commonly electrically connected to ground potential in order that the isolation p-n junctions be reverse-biased.
Vertical pnp transistors fabricated in silicon based bipolar monolithic ICs with epitaxy and diffusion processes include a heavily doped p.sup.+ buried collector that is isolated from the p-substrate by an n buried layer. This geometry results in an outer epitaxial (epitaxial is hereinafter abbreviated as "epi") region that is isolated from the epi region that forms the base of the device. Known techniques for biasing the outer epi region of a vertical pnp transistor include electrically connecting the same to the collector of the vertical pnp transistor or to the supply, or allowing the same to float.
Conventionally the outer epi region of a vertical pnp transistor is electrically connected to its collector to eliminate the possibility of activation of parasitic devices. However, in this configuration a short to -2 V on the collector will forward bias the outer epi to substrate diode, resulting in excessive current from the output being pulled through the substrate and possibly producing improper circuit operation including latch up.
Improper circuit operation from a short to ground may be avoided by allowing the potential of the outer epi to float. The collector could now go below ground potential without risk of the outer epi forward biasing through the substrate. Unfortunately, when the collector is at a high potential, reverse bias leakage current from the outer epi to the substrate will act as the base current to a parasitic pnp transistor. This parasitic transistor then begins to conduct and pulls current from the output at the same time the output transistor is engaged in sourcing current to the output load, a clearly undesirable and intolerable condition that substantially worsens at higher temperatures as a result of increased leakage current.
U.S. Pat. No. 4,577,211 to Bynum et al., teaches the active biasing of an epi pocket, containing p regions tied to supply, in order to protect against said p regions going below ground. However, it does not address having two p regions in an epi pocket with one tied to supply and the other p region tied to an output that can be shorted to a voltage greater than supply Additionally, it is known that improper circuit operation from a short to ground also may be avoided by electrically connecting the outer epi to the supply, which as previously noted is also electrically connected to the emitter. In this configuration the collector can be taken below the p-substrate ground potential and any outer epi to substrate reverse bias leakage current would get pulled out of the supply. However, if the collector of the vertical pnp transistor was shorted to battery at the same time supply is at ground potential (which means that the emitter of the vertical pnp transistor, also electrically connected to supply, is at ground potential), the parasitic pnp transistor would turn on and conduct current to the p-substrate. This could damage the load or destroy the IC.
Thus, for the common vertical pnp transistor electrically connected in the common output configuration, all possible passive biasing arrangements allow unacceptable operation or produce significant damage in the event of one or more types of faults.